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課程名稱 |
交換電路與邏輯設計
Switching Circuit and Logic Design |
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開課學期 |
100-1 |
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授課對象 |
電機工程學系 |
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授課教師 |
盧奕璋 |
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課號 |
EE2012 |
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課程識別碼 |
901 32300 |
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班次 |
01 |
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學分 |
3 |
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全/半年 |
半年 |
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必/選修 |
必修 |
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上課時間 |
星期四6(13:20~14:10)星期五7,8(14:20~16:20) |
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上課地點 |
電二143電二143 |
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備註 |
本系優先
總人數上限：70人 |
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Ceiba 課程網頁 |
http://ceiba.ntu.edu.tw/1001SCLD |
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課程簡介影片 |
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核心能力關聯 |
核心能力與課程規劃關聯圖 |
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課程大綱
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為確保您我的權利,請尊重智慧財產權及不得非法影印
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課程概述 |
1. Introduction: Number Systems and Conversion
2. Boolean Algebra
3. Boolean Algebra (continued)
4. Applications of Boolean Algebra: Minterm and Maxterm Expansions
5. K-Maps
6. Multi-Level Gate Circuits: NAND and NOR Gates
7. Combinational Circuit Design and Simulation Using Gates
8. Multiplexers, Decodes and PLD
9. Introduction to Verilog-HDL
10. Latches and FFs
11. Registers and Counters
12. Analysis of Clocked Sequential Circuits
13. Derivation of State Graphs and Tables
14. Reduction of State Tables-- State assignment
15. Sequential Circuit Design
16. Circuits for Arithmetic Operations
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課程目標 |
Provide essential knowlege of switching circuit and logic design. |
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課程要求 |
6 Homeworks, 2 Quizs, 1 Midterm, 1 Final |
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預期每週課後學習時數 |
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Office Hours |
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指定閱讀 |
C. H. Roth, Jr. and L. L. Kinney, Fundamentals of Logic Design, 6th edition, CENGAGE Learning, 2009. |
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參考書目 |
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評量方式
(僅供參考) |
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No. |
項目 |
百分比 |
說明 |
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1. |
Homework |
18% |
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2. |
Quiz1 |
4% |
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3. |
Midterm |
35% |
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4. |
Quiz2 |
6% |
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5. |
Final |
35% |
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6. |
Participation |
2% |
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週次 |
日期 |
單元主題 |
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第1週 |
9/15,9/16 |
Ch 1 Introduction: Number Systems and Conversion
Ch 2 Boolean Algebra |
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第2週 |
9/22,9/23 |
Ch 2 Boolean Algebra
Ch 3 Boolean Algebra (cont'd) |
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第3週 |
9/29,9/30 |
Ch 4 Application of Boolean Algebra |
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第4週 |
10/06,10/07 |
Ch 5 Karnaugh Maps |
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第5週 |
10/13,10/14 |
Ch 7 Multi-Level Gate Circuits: NAND and NOR Gates |
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第6週 |
10/20,10/21 |
Quiz 1 (Ch 1-5)
Ch 8 Combinational Ckt Design (skip 8.1, 8.2) |
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第7週 |
10/27,10/28 |
Ch 8 (cont'd)
Ch 9 Multiplexers Decoders and PLD (skip 9.7) |
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第8週 |
11/03,11/04 |
Ch 9 (cont'd)
Verilog: Combinational Circuits (3:30-6:00pm) |
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第9週 |
11/10,11/11 |
No Class
Midterm Exam |
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第10週 |
11/17,11/18 |
Ch 11 Latches and FFs |
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第11週 |
11/24,11/25 |
Ch 12 Registers and Counters |
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第12週 |
12/01,12/02 |
Ch 13 Analysis of Clock Sequential Ckts |
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第13週 |
12/08,12/09 |
Ch 14 Derivation of State Graphs and Tables
(Skip examples 2 & 3 in Sec. 14.3) |
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第14週 |
12/15,12/16 |
Quiz 2 (Ch 11-13)
Ch 15 Reduction of State Tables (15.1 to 15.2) |
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第15週 |
12/22,12/23 |
Ch 16 Sequential Ckt Design (16.1 to 16.4) |
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第16週 |
12/29,12/30 |
Ch 18 Circuits for Arithmetic Operations (18.1-18.2) |
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第17週 |
1/05,1/06 |
Supplementary Materials |
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第18週 |
1/13 |
Final Exam |
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